1. Field of the Invention
This invention relates to semiconductor fabrication and more particularly to a dielectric material placed between semiconductor interconnect lines on the same or on different levels such that the dielectric contains air gaps and trenches arranged between interconnect lines. The air gaps or trenches are void of dielectric thereby decreasing the overall permittivity of the interlevel or interlayer dielectric.
2. Description of the Relevant Art
An integrated circuit includes numerous conductors extending across the topography of a monolithic substrate. A set of interconnect lines (or conductors) which serve to electrically connect two or more components within a system is generally referred to as a "bus". A collection of voltage levels are forwarded across the conductors to allow proper operation of the components. For example, a microprocessor is connected to memories and input/output devices by certain bus structures. There are numerous types of busses which are classified according to their operation. Examples of well-known types of busses include address busses, data busses and control busses.
Conductors within a bus generally extend parallel to each other across the semiconductor topography. The conductors are isolated from each other and from underlying conductive elements by a dielectric, a suitable dielectric being, for example, silicon dioxide ("oxide"). Conductors are thereby lithography patterned across the semiconductor topography, wherein the topography comprises a substrate with a dielectric placed thereon. The topography can also include one or more layers of conductors which are sealed by an upper layer of dielectric material. Accordingly, the layers of conductors overlayed with a dielectric present a topography upon which a subsequent layer of conductors can be patterned.
Conductors are made from an electrically conductive material. Suitable materials may include Al, Ti, Ta, W, Mo, polysilicon, or a combination thereof. Suitable substrates may include any type of material which can retain dopant ions and the isolated conductivity regions brought about by those ions. Typically, the substrate is a silicon-based material which receives p-type or n-type ions.
Generally speaking, interconnect lines (or conductors) are fashioned upon the topography and spaced above an underlying conductor or substrate by a dielectric of thickness T.sub.d1. Each conductor is dielectrically spaced from other conductors within the same level of conductors by a distance T.sub.d2. Accordingly, conductor-to-substrate capacitance C.sub.LS (i.e., capacitance between conductors on different levels) is determined as follows: EQU C.sub.LS.apprxeq..epsilon.W.sub.L L/T.sub.d1 (1)
Further, the conductor-to-conductor capacitance C.sub.LL (i.e., capacitance between conductors on the same level) is determined as follows: EQU C.sub.LL.apprxeq..epsilon.T.sub.c L/T.sub.d2 (2)
, where .epsilon. is the permittivity of the dielectric material (the dielectric material between the conductor and substrate or the dielectric material between conductors), W.sub.L is the conductor width, T.sub.c is the conductor thickness, and L is the conductor length. Resistance of the conductor is calculated as follows: EQU R=(pL)/W.sub.L T.sub.c (3)
, where p represents resistivity of the conductive material, and T.sub.c is the interconnect thickness. Combinations of equations 1 and 3, and/or equations 2 and 3 indicate the propagation delay of a conductor as follows: EQU RC.sub.LS.apprxeq.p.epsilon.L.sup.2 /T.sub.c T.sub.d1 EQU RC.sub.LL.apprxeq.p.epsilon.L.sup.2 /W.sub.L T.sub.d2
Propagation delay is an important characteristic of an integrated circuit since it limits the speed (frequency) at which the circuit or circuits can operate. The shorter the propagation delay, the higher the speed of the circuit or circuits. It is therefore important that propagation delay be minimized as much as possible within the geometric constraints of the semiconductor topography.
Propagation delay is a function of both capacitance C.sub.LS as well as capacitance C.sub.LL. Accordingly, propagation delay is determined by parasitic capacitance values (C.sub.LL) between laterally spaced conductors, and parasitic capacitance values (C.sub.LS) between vertically spaced conductors or between a conductor and the underlying substrate. As circuit density increases, lateral spacing between conductors decrease and capacitance C.sub.LL increases. Meanwhile, planarization mandates to some extent a decrease in vertical spacing. Shallow trench processing, recessed LOCOS processing, and multi-layered interlevel dielectrics bring about an overall reduction in vertical spacing and therefore an increase in C.sub.LS. Integrated circuits which employ narrow interconnect spacings thereby define C.sub.LL as a predominant capacitance, and integrated circuits which employ thin interlevel dielectrics define C.sub.LS as a predominant capacitance.
It is thereby important to minimize propagation delay especially in the critical speed path. Given the constraints of chemical compositions, it is not readily plausible to reduce the resistivity p of conductor materials. Geometric constraints make it difficult to increase conductor thickness T.sub.c or dielectric thickness T.sub.d1 or T.sub.d2. Still further, instead of reducing length L of a conductor, most modern integrated circuits employ long interconnect lines which compound the propagation delay problems. Accordingly, a need arises for instituting a reduction in propagation delay but within the chemical and geometric constraints of existing fabrication processes. It is therefore desirable that a fabrication process be developed which can reduce propagation by reducing the permittivity .epsilon. of dielectric material. More specifically, the desired process must be one which reduces the permittivity of dielectric material arranged between horizontally displaced or vertically displaced conductors. As such, it would be desirable to employ a fabrication technique in which dielectrics between conductors achieve low permittivity.